1. Field of the Invention
This invention relates generally to the field of semiconductor device manufacturing and, more particularly, to a method and apparatus for dynamic adjustment of a sampling plan based on wafer electrical test data.
2. Description of the Related Art
A variety of processing tools are used to fabricate a semiconductor device. The processing tools may include photolithography steppers, etch tools, deposition tools, polishing tools, rapid thermal processing tools, ion implantation tools, and the like. Wafers and/or wafer lots, collectively referred to hereinafter as workpieces, are processed in the tools in a predetermined order and each processing tool modifies the workpieces according to a particular operating recipe. For example, a photolithography stepper may be used to form a patterned layer of photoresist (i.e. a mask) above a layer of gate electrode material that has been deposited above a wafer. Features in the patterned layer of photoresist correspond to a plurality of features, e.g. gate electrode structures, which will ultimately be formed above the surface of the wafer in the layer of gate electrode material.
The performance of individual processing tools is typically monitored using one or more sensors to collect data associated with operation of the processing tool. For example, an etching tool may include a sensor to monitor the radio frequency power delivered by the etching tool. For another example, a rapid thermal anneal tool may include a thermocouple to monitor a temperature within the tool. The data acquired by the various sensors may be referred to as tool trace data. The collected tool trace data may be used for various purposes such as fault detection and/or classification. For example, the tool trace data collected by the thermocouple in the rapid thermal anneal tool may indicate that the temperature within the tool has dropped below a desired threshold, indicating a possible fault.
The performance of individual processing tools may also be monitored using one or more integrated metrology tools to collect wafer state data indicative of the physical state of one or more wafers processed in the processing tool. For example, one or more integrated metrology tools may be used to perform measurements on selected wafers after they have been processed by one or more processing tools. The integrated metrology tools may include scatterometers, ellipsometers, temperature sensors, and the like. The measurements may include measurements of a temperature of a wafer, a thickness of a layer of material formed on the wafer, a critical dimension (CD) of one or more features formed on the wafer, a profile of one or more features formed on the wafer, and the like. The measurements may be performed in situ or ex situ, depending on the type of integrated metrology tool.
Wafer electrical tests are also performed on wafers to collect data related to anticipated yield and/or electrical performance of the devices formed on the wafers. The wafer electrical tests typically test logical and/or electrical properties of the devices. Some wafer electrical tests operate on a device level. For example, one wafer electrical test may test the switching speed of individual transistors on a die, an electrical path on the die, a word line in a memory device, and the like. Wafer electrical tests also test integrated circuits on an operational level. For example, a wafer electrical test may be used to assess the processing speed and/or accuracy of logical operations performed by a microprocessor. For another example, a wafer electrical test may be used to assess the read/write speed and/or stability of a flash memory device.
Faults in the processing tools may degrade the performance of the devices formed on wafers processed by the faulty processing tools, and in some cases may lead to device failures that force the finished products to be reworked or discarded. Some faults may be detected using the sensors or integrated metrology tools, which may permit the fault to be corrected or compensated for in subsequent processing. However, other faults are not detected until the finished product undergoes wafer electrical testing. Although the wafer electrical test data may include information indicative of the faults that may be used to correct or compensate for the fault, these tests are typically performed weeks or months after the devices are formed on the workpieces. Consequently, wafer electrical test data can not easily be used to detect and/or correct faulty processing.
The present invention is directed to addressing the effects of one or more of the problems set forth above.